Although microcomputers (which include, in one integrated circuit, RAM and various dedicated functions, in addition to the central processing unit itself) are well known in the art, the process of designing such devices has been geared toward producing standard off-the-shelf products which generally meet the public's needs. The architectures underlying such devices have not been designed to be customized to fit the needs of particular users. Rather, they have been designed to perform optimally for a predetermined set of macroinstructions.
Examples of such microcomputers include the Intel 8031/8051, the architecture of which is specified in Chapter 6 of the 1984 Intel Microcontroller Handbook (Order No. 210918-002), and the Programmable Single Chip MOS Computer disclosed in U.S. Pat. Nos. 4,153,933 and 4,306,163. From what one can discern from the descriptions of these devices (and all other microcomputer architectures known to the inventors), it is clear that their architectures are rigid and inflexible. Memory sizes for code and data, macroinstruction decoding and timing, and even the available peripheral functions (such as timers/counters and serial controllers), are all predetermined and not capable of change.
This is not surprising given the traditional approach to microcomputer architecture design. As a general rule, the microcomputer user is concerned only with its external interface--e.g., the macroinstruction set and pin definitions, perhaps including the timing required to execute each instruction. In other words, the user is concerned only with which operations the chip performs, not how it performs those operations.
Thus, previous microcomputer architectures consist of minimized logic paths designed to optimize the performance of the device for its predetermined functions. In other words, the microarchitecture is designed with one purpose in mind--executing the specified instruction set as quickly as possible for a given integrated circuit area. No thought is given to the possibility that the same architecture might be reused for a slightly (or perhaps significantly different) application.
As is the case with any "standard device," many potential users would prefer to play a role in the design process itself, and to customize the device to suit their individual requirements. Short of designing a custom microcomputer for each such user, however, there does not currently exist a method of providing users with a customizable microcomputer that suits their individual needs.
An additional problem relates to the testing of that on-chip memory independently from the CPU. When an entire microcomputer (including memory) is fabricated on one integrated circuit, it becomes quite difficult to test the memory independently from the rest of the circuit.
One method of solving this problem is described in U.S. Pat. No. 4,153,933, in which special instructions cause program ROM to be sourced onto the main internal bus, independently of the CPU operation (particularly the program counter). This method, however, still utilizes the main internal bus, necessitating the design of dedicated logic to address the ROM. This dedicated logic is not without costs, both in the speed of normal execution and in silicon area. Even more significantly, when varying memory sizes are permitted, the problems associated with the design of this dedicated logic are exacerbated (because multiple sets of dedicated logic must be created).